Field of the Invention
The present invention generally relates to a multi-core processor, and more specifically, to a system for controlling gatings of a multi-core processor and a multi-core processor.
Description of the Related Art
With the development of computer technology, a multitask environment is generally involved when a computer is used by a user, wherein multi-media tasks such as games have more and more requirements for performance of a processor. A traditional single-core processor cannot meet the computing performance requirement of new applications which is increasingly developed because of the restriction of performance and manufacturing process, and the like. The processing capacity of a multi-core processor is significantly better than that of a single-core processor. A “horizontal scalability” method is involved by multi-core processor technology, wherein an application is divided into multiple threads which are assigned to a number of processing engines within a multi-core processor to execute in parallel, thereby providing a new solution for performance problem. Graphics processing unit (GPU) is a typical multi-core processor, for example, there are thousands of parallel processing engines (CUDA Core) in GPU architecture of Nvidia.
During normal operation of a multi-core processor, the loads on it change with different processing tasks. The load change could lead to significant current transient in the multi-core processor because the multi-core processor contains billions of transistors. A GPU current transient frequency could typically be in a range of 1 KHz˜16 KHz and then leads to vibration of output inductors of a DC-DC power regulator at a corresponding frequency. This vibration may be amplified and transformed into annoying acoustics noise by a printed circuit board (PCB). Moreover, the die temperature of a multi-core processor might be rising up to 6° C. per second while the multi-core processor starts running an application from idle. Because of the sharply increasing of the temperature, the bump/ball of the multi-core processor package might be cracked due to different thermal expansion of materials. Furthermore, the above described current transient could result in voltage noise in the multi-core processor. In order to solve the above problems, the clock frequency of a multi-core processor is generally reduced to decrease the amplitude of load transient and the influence thereof in turn in the prior art. However, the processing performance degradation of the multi-core processor could be incurred because the clock frequency is reduced.
Therefore, what is needed in the art is a system for decreasing the amplitude of load transient without the performance degradation when the load change happens on a multi-core processor, thereby solving the above problems.